Method of manufacturing semiconductor memory device

ABSTRACT

A nonvolatile semiconductor memory device includes a semiconductor substrate, a first floating gate formed on a main surface of the semiconductor substrate, a second floating gate formed on the main surface of the semiconductor substrate, a first control gate formed on the first floating gate, a second control gate formed on the second floating gate, an interlayer insulating film, and a gap formed in the interlayer insulating film in at least a portion located between the first and second floating gates. Accordingly, a nonvolatile semiconductor memory device for which variations in threshold voltage of a memory cell can be suppressed and an appropriate read operation can be carried out, as well as a method of manufacturing the nonvolatile semiconductor memory device are provided. Further, a capacitance formed between interconnect lines can be reduced and the drive speed can be improved.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a nonvolatile semiconductor memorydevice and a semiconductor device as well as a method of manufacturing anonvolatile semiconductor memory device.

2. Description of the Background Art

The nonvolatile semiconductor memory device and the semiconductor devicehave been miniaturized and downsized. As the nonvolatile semiconductormemory device is miniaturized, the spacing between floating gates isdecreased and a capacitance formed between the floating gates adjacentto each other is increased. Therefore, in a read operation, a change inamount of electric charge accumulated in a floating gate adjacent to afloating gate of a selected memory cell causes a similar phenomenon tothe phenomenon that occurs in the case where electric charge is injectedinto the floating gate of the selected memory cell. Accordingly, thethreshold voltage of the selected memory cell varies, which results in aproblem of difficulty in accurately reading electrical information ofthe selected memory cell. Further, as the semiconductor device isminiaturized, the spacing between interconnect lines provided in thesemiconductor device is decreased and a capacitance between theinterconnect lines is increased, which results in a problem that theprocessing speed of the semiconductor device decreases.

Under the circumstances, various semiconductor devices having adecreased capacitance between interconnect lines have recently beenproposed. For example, Japanese Patent Laying-Open No. 2000-353740discloses a semiconductor device having a semiconductor substrate, aplurality of interconnect lines formed on a main surface of thesemiconductor substrate, an insulating film formed on the top surface ofthe interconnect line and having a larger width than the interconnectline, and an interlayer insulating film formed to cover the interconnectlines each.

In such a semiconductor device, the insulating film formed on theinterconnect line forms an overhang, namely projecting edge, whichfacilitates formation of a gap in the interlayer insulating film in aregion between interconnect lines, and accordingly the capacitanceformed between the interconnect lines is decreased. Further, JapanesePatent Laying-Open No. 2001-217310 discloses a semiconductor devicehaving a semiconductor substrate, a plurality of interconnect linesformed via a first electrically conductive film on a main surface of thesemiconductor substrate, a second electrically conductive film formed onthe top surface of the interconnect line and larger in width than theinterconnect line, and an interlayer insulating film formed to cover theinterconnect lines.

In such a semiconductor device, the second electrically conductive filmforms an overhang, a gap is formed in the interlayer insulating film ina region between interconnect lines, and accordingly a capacitancebetween the interconnect lines is decreased. Furthermore, JapanesePatent Laying-Open No. 2001-085519 discloses a semiconductor devicehaving an interconnect line formed with its width increasing as theupward distance from the top of a main surface of a semiconductorsubstrate increases and an interlayer insulating film formed to coverthe interconnect line.

In this semiconductor device, the top surface of the interconnect linehas an overhang as formed and a gap is formed between interconnectlines. The capacitance formed between the interconnect lines is thusdecreased.

SUMMARY OF THE INVENTION

In the above-described conventional semiconductor devices, allinterconnect lines have overhang portions formed to extend in thelongitudinal direction of the interconnect lines. Therefore, an air gapis also formed in a region where the spacing between interconnect linesis large. In the case where the air gap is formed in the region wherethe spacing between interconnect lines is large, the interlayerinsulating film could not completely close the top end portion of theair gap to accordingly form an opening. In such a case where the openingof the air gap is formed in the interlayer insulating film, a resultantproblem is that, in a subsequent cleaning process, a cleaning fluidcould enter the air gap. Moreover, the conventional nonvolatilesemiconductor memory has the problem, as described above, that an amountof electric charge accumulated in the floating gate located around aselected memory cell could cause the threshold voltage of the selectedmemory cell to vary.

The present invention is made in consideration of the aforementionedproblems. An object of the present invention is to provide a nonvolatilesemiconductor memory device in which variations of the threshold voltageof a memory cell are suppressed as well as a method of manufacturing thenonvolatile semiconductor memory device, and to provide a semiconductordevice decreased in capacitance between interconnect lines and increasedin drive speed.

A nonvolatile semiconductor memory device according to the presentinvention includes: a semiconductor substrate; a first floating gateformed on a main surface of the semiconductor substrate with a firstelectrically insulating film therebetween; a second floating gate formedon the main surface of the semiconductor substrate with a secondelectrically insulating film therebetween; a first control gate formedon the first floating gate with a third electrically insulating filmtherebetween and having a first wider portion larger than the firstfloating gate in width in the direction parallel with the main surfaceof the semiconductor substrate; a second control gate formed on thesecond floating gate with a fourth electrically insulating filmtherebetween and having a second wider portion larger than the secondfloating gate in width in the direction parallel with the main surfaceof the semiconductor substrate; an interlayer insulating film formed tocover the first control gate and the second control gate; and a gapformed in the interlayer insulating film in at least a portion locatedbetween the first floating gate and the second floating gate.

A semiconductor device according to the present invention includes: asemiconductor substrate; a first interconnect line formed on a mainsurface of the semiconductor substrate with a first electricallyinsulating film therebetween; a second interconnect line formed on themain surface of the semiconductor substrate with a second electricallyinsulating film therebetween to extend along the first interconnectline; a first electrically conductive film formed on a top surface ofthe first interconnect line and formed to be larger than the firstinterconnect line in width in the direction parallel with the mainsurface of the semiconductor substrate; a second electrically conductivefilm formed on a top surface of the second interconnect line and formedto be larger than the second interconnect line in width in the directionparallel with the main surface of the semiconductor substrate; a thirdelectrically insulating film formed to cover the first electricallyconductive film and the second electrically conductive film; a gapformed in the third electrically insulating film in at least a portionlocated between the first interconnect line and the second interconnectline; a first region where the distance between the first interconnectline and the second interconnect line is at most a predetermined value;and a second region where the distance between the first interconnectline and the second interconnect line is larger than the predeterminedvalue. The first electrically conductive film and the secondelectrically conductive film are formed in the first region.

A method of manufacturing a nonvolatile semiconductor memory deviceaccording to the present invention includes the steps of: forming afirst floating gate on a main surface of a semiconductor substrate witha first electrically insulating film therebetween and forming a secondfloating gate on the main surface of the semiconductor substrate with asecond electrically insulating film therebetween; forming a firstcontrol gate on a top surface of the first floating gate with a thirdelectrically insulating film therebetween and forming a second controlgate on a top surface of the second floating gate with a fourthelectrically insulating film therebetween; forming a first wider portionof the first control gate by reducing, in film size in the directionparallel with the main surface of the semiconductor substrate, the firstfloating gate and a part of the first control gate, the first widerportion being larger, in width in the direction parallel with the mainsurface of the semiconductor substrate, than the first floating gatereduced in film size; forming a second wider portion of the secondcontrol gate by reducing, in film size in the direction parallel withthe main surface of the semiconductor substrate, the second floatinggate and a part of the second control gate, the second wider portionbeing larger, in width in the direction parallel with the main surfaceof the semiconductor substrate, than the second floating gate reduced infilm size; and forming an interlayer insulating film covering the firstcontrol gate and the second control gate, allowing a portion of theinterlayer insulating film that covers the first wider portion tocontact a portion of the interlayer insulating film that covers thesecond wider portion, and forming a gap between the floating gates.

With the nonvolatile semiconductor memory device and the method ofmanufacturing the nonvolatile semiconductor memory device according tothe present invention, variations in threshold voltage of a memory cellcan be suppressed, an appropriate read operation is carried out.Further, with the semiconductor device according to the presentinvention, a capacitance formed between interconnect lines can bereduced and the drive speed can be improved.

The foregoing and other objects, features, aspects and advantages of thepresent invention will become more apparent from the following detaileddescription of the present invention when taken in conjunction with theaccompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a plan view of a nonvolatile semiconductor memory deviceaccording to a first embodiment.

FIG. 2 a cross-sectional view along line II-II in FIG. 1.

FIG. 3 is a cross-sectional view along line III-III in FIG. 1.

FIG. 4 is a cross-sectional view illustrating a write operation of thenonvolatile semiconductor memory device.

FIG. 5 is a cross-sectional view illustrating a read operation of thenonvolatile semiconductor memory device.

FIG. 6 is a cross-sectional view of the nonvolatile semiconductor memorydevice in an erase operation.

FIGS. 7 to 12 are cross-sectional views illustrating first to sixthsteps respectively of a manufacturing process of the nonvolatilesemiconductor memory device according to the first embodiment.

FIG. 13 is a cross-sectional view of a portion along assist gates AGshown in FIG. 1 and between assist gates AG formed in the sixth step.

FIGS. 14 and 15 are cross-sectional views illustrating seventh andeighth steps respectively of the manufacturing process of thenonvolatile semiconductor memory device according to the firstembodiment.

FIG. 16 is a plan view of a semiconductor device according to a secondembodiment.

FIG. 17 is a plan view of a region different from the region shown inFIG. 16.

FIG. 18 is a cross-sectional view along line XVIII-XVIII in FIG. 16.

FIG. 19 is a cross-sectional view along line XIX-XIX in FIG. 16.

FIG. 20 is a cross sectional view along line XX-XX in FIG. 17.

FIG. 21 is a cross-sectional view illustrating a first step of amanufacturing process of the semiconductor device.

FIG. 22 is a cross-sectional view of a region different from the regionin FIG. 21, illustrating the first step of the manufacturing process ofthe semiconductor device.

FIG. 23 is a cross-sectional view of a region different from thoseregions in FIGS. 21 and 22, illustrating the first step of themanufacturing process of the semiconductor device.

FIG. 24 is a cross-sectional view subsequent to the step shown in FIG.21, illustrating a second step of the manufacturing process of thesemiconductor device.

FIG. 25 is a cross-sectional view subsequent to the step shown in FIG.22, illustrating the second step of the manufacturing process of thesemiconductor device.

FIG. 26 is a cross-sectional view subsequent to the step shown in FIG.23, illustrating the second step of the manufacturing process of thesemiconductor device.

FIG. 27 is a cross-sectional view illustrating a third step of themanufacturing process of the semiconductor device.

FIG. 28 is a cross-sectional view of a region different from the regionin FIG. 27, illustrating the third step of the manufacturing process ofthe semiconductor device.

FIG. 29 is a cross sectional view of a region different from thoseregions in FIGS. 27 and 28, illustrating the third step of themanufacturing process of the semiconductor device.

FIG. 30 is a cross-sectional view illustrating a fourth step of themanufacturing process of the semiconductor device.

FIG. 31 is a cross-sectional view of a region different from the regionin FIG. 30, illustrating the fourth step of the manufacturing process ofthe semiconductor device.

FIG. 32 is a cross-sectional view of a region different from thoseregions in FIGS. 30 and 31, illustrating the fourth step of themanufacturing process of the semiconductor device.

FIG. 33 is a circuit diagram showing a general AND-type flash arrayconfiguration.

FIG. 34 is a cross-sectional view of a memory cell transistor.

FIG. 35 is a circuit diagram showing a general NAND-type flash arrayconfiguration.

FIG. 36 is a detailed cross-sectional view of a memory cell transistor.

DESCRIPTION OF THE PREFERRED EMBODIMENTS First Embodiment

With reference to FIGS. 1 to 15, a nonvolatile semiconductor memorydevice 100 according to a first embodiment is described. FIG. 1 is aplan view of nonvolatile semiconductor memory device 100 according tothe first embodiment. As shown in FIG. 1, on a main surface of asemiconductor substrate 1, a plurality of assist gates AG spaced fromeach other extend in the same direction, and a plurality of controlgates CG spaced from each other extend in a direction crossing assistgates AG. Further, in a region that is located between assist gates AGand located on the main surface of semiconductor substrate 1 and undercontrol gates CG, floating gates FG are formed. Thus, on the mainsurface of semiconductor substrate 1, a plurality of memory cells MC areformed. Further, on the main surface of semiconductor substrate 1, airgaps GA are formed between floating gates FG that are adjacent to eachother in the direction in which assist gates AG extend.

FIG. 2 is a cross-sectional view along line II-II in FIG. 1. As shown inFIG. 2, nonvolatile semiconductor memory device 100 includessemiconductor substrate 1, assist gates AG formed on the main surface ofsemiconductor substrate 1 with an electrically insulating film 8therebetween, floating gates FG formed on the main surface ofsemiconductor substrate 1 with an electrically insulating film 15therebetween, and control gates CG formed on the top surface of floatinggates FG with an electrically insulating film 18 therebetween. Assistgates AG are formed for example of a low-resistance polycrystallinesilicon film. Insulating film 8 formed under assist gates AG is made forexample of silicon oxide and has a thickness of approximately 8.5 nm interms of the thickness of silicon dioxide.

On the side surface of assist gates AG, an electrically insulating film9 made for example of silicon oxide is formed. Further, on the topsurface of assist gates AG, an electrically insulating film 10 made forexample of silicon nitride (such as Si₃N₄) is formed.

Control gate CG is formed of a multilayered film comprised of anelectrically conductive film CGa made for example of low-resistancepolycrystalline silicon and an electrically conductive film CGb formedon the top surface of conductive film CGa and formed for example of sucha refractory-metal silicide film as tungsten silicide (WSi_(x)).

Floating gate FG is a charge storage layer for data of memory cell MC asdescribed above and made for example of low-resistance polycrystallinesilicon.

On the main surface of semiconductor substrate 1 and under floating gateFG, insulating film 15 serving as a tunnel insulating film of memorycell MC is formed. Insulating film 15 is made for example of siliconoxide-nitride (SiON).

Between assist gate AG and floating gate FG, insulating film 9 and aninsulating film 16 are formed to electrically insulate assist gate AGand floating gate FG from each other. Insulating film 16 is made forexample of silicon oxide. Insulating film 18 is formed for example of aso-called ONO film comprised for example of silicone oxide, siliconnitride and silicon oxide deposited in this order from the lowest layer.Insulating film 18 has a thickness of approximately 16 nm for example interms of the thickness of silicon dioxide.

FIG. 3 is a cross-sectional view along line III-III in FIG. 1, which isa cross section in the direction orthogonal to the direction of controlgate CG. As shown in FIG. 3, on the main surface of semiconductorsubstrate 1, a floating gate (first floating gate) FGa formed withinsulating film (first insulating film) 15 therebetween, and a floatinggate (second floating gate) FGb formed with insulating film 15therebetween and located adjacent to floating gate FGa are provided, andan interlayer insulating film 17 is formed to cover control gates CG1,CG2. In interlayer insulating film 17, in a region located betweenfloating gates FGa and FGb, air gap GA is formed.

Further, on the top surface of floating gate FGa, control gate CG1 isformed with an electrically insulating film 18 a therebetween. On thetop surface of floating gate FGb, control gate CG2 is formed with anelectrically insulating film 18 b therebetween.

Control gate CG1 includes an electrically conductive film CGa1 formed onthe top surface of floating gate FGa with insulating film 18 atherebetween, and an electrically conductive film CGa2 formed on the topsurface of conductive film CGa1. Control gate CG2 includes anelectrically conductive film CGb1 formed on the top surface of floatinggate FGb with insulating film 18 b therebetween, and an electricallyconductive film CGb2 formed on the top surface of conductive film CGb2.

Conductive film CGa1 has width Ma2 that is in the direction parallelwith the main surface of semiconductor substrate 1 and that is largerthan width Ma1 of floating gate FGa that is in the direction parallelwith the main surface of semiconductor substrate 1. Conductive film CGa2has width Ma3 in the direction parallel with the main surface ofsemiconductor substrate 1 that is smaller than the width of conductivefilm CGa1. Further, conductive film CGb1 has width Mb2 in the directionparallel with the main surface of semiconductor substrate 1 that islarger than width Mb1 of floating gate FGb that is in the directionparallel with the main surface of semiconductor substrate 1. Conductivefilm CGb2 has width Mb3 in the direction parallel with the main surfaceof semiconductor substrate 1 that is smaller than width Mb2 ofconductive film CGb1 that is in the direction parallel with the mainsurface of semiconductor substrate 1.

Thus, control gate CG1 has a wider portion 28 a having its width largerthan width Mal of floating gate FGa that is in the direction parallelwith the main surface of semiconductor substrate 1. Further, controlgate CG2 has a wider portion 28 b having its width larger than width Mb1of floating gate FGb that is in the direction parallel with the mainsurface of semiconductor substrate 1. Here, insulating films 18 a, 18 bare formed to have respective widths larger than widths Ma1, Mb1 offloating gates FGa, FGb that are in parallel with the main surface ofsemiconductor substrate 1.

Accordingly, on the top surface of floating gate FGa, an overhangportion 38 a is formed that is comprised of conductive film CGa1 andinsulating film 18 a and has its width larger than width Ma1 of floatinggate FGa that is in the direction parallel with semiconductor substrate1. Further, on the top surface of floating gate FGb, an overhang portion38 b is formed that is comprised of conductive film CGb1 and insulatingfilm 18 b and has its width larger than width Mb1 of floating gate FGbthat is in the direction parallel with semiconductor substrate 1. In thefirst embodiment, the width of overhang portions 38 a, 38 b and thewidth of wider portions 28 a, 28 b are identical to each other, and thewidth of overhang portions 38 a, 38 b in the direction parallel with themain surface of semiconductor substrate 1 is larger by approximately 15nm than the width of floating gates FGa, FGb. Thus, the distance betweenoverhang portions 38 a and 38 b in the direction parallel with the mainsurface of semiconductor substrate 1 is smaller than the distancebetween floating gates FGa and FGb.

Interlayer insulating film 17 is formed slightly on the main surface ofsemiconductor substrate 1 and also formed on the side surfaces offloating gates FGa, FGb. Interlayer insulating film 17 formed on theside surfaces of floating gates FGa, FGb has its width in the directionparallel with the main surface of semiconductor substrate 1 and thewidth increases as the upward distance from the substrate increases. Ininterlayer insulating film 17, those portions respectively coveringoverhang portions 38 a, 38 b contact each other, and the space betweenoverhang portions 38 a and 38 b and the space between control gates CG1and CG2 are filled with interlayer insulating film 17. Interlayerinsulating film 17 is formed for example of a silicon oxide film.

Air gap GA is formed in interlayer insulating film 17 in a portionlocated under the region of contact between the portion of interlayerinsulating film 17 covering overhang portion 38 a and the one coveringoverhang portion 38 b. Air gap GA is formed to extend from a portion onthe main surface of semiconductor substrate 1 over the region betweenfloating gates FGa and FGb. The top end of air gap GA is located nearthe bottom end of overhang portions 38 a, 38 b. Air gap GA has its widthin the direction parallel with the main surface of semiconductorsubstrate 1 that is made smaller as the distance from the top of themain surface of semiconductor substrate 1 increases, and is closed onthe bottom surface of overhang portions 38 a, 38 b.

Thus, between floating gates FGa and FGb adjacent to each other in thedirection orthogonal to the direction in which control gates CG1, CG2extend, air gap GA is formed and accordingly, the capacitance formedbetween floating gates FGa and FGb is reduced.

A write operation, a read operation and an erase operation ofnonvolatile semiconductor memory device 100 configured as describedabove are now described. FIG. 4 is a cross-sectional view illustratingthe write operation of nonvolatile semiconductor memory device 100. Asshown in FIG. 4, to a control gate CG to which a selected memory cell MCis connected, a voltage of approximately 15 V for example is appliedand, to other control gates CG, a voltage of approximately 0 V forexample is applied. Further, to an assist gate AG2 for forming thesource of the selected memory cell MC, a voltage of approximately 1 Vfor example is applied and, to an assist gate AG3 for forming the drain,a voltage of approximately 7 V for example is applied. To other assistgates AG1, AG4, a voltage of approximately 0 V for example is applied.Accordingly, at the main surface of semiconductor substrate 1 locatedunder assist gate AG2 for forming the source, an n-type inverted layer23 a serving as the source is formed. At the main surface ofsemiconductor substrate 1 located under assist gate AG3 for forming thedrain, an n-type inverted layer 23 b serving as the drain is formed. Itis noted that the voltage of approximately 0 V is applied to otherassist gates AG1, AG4 to prevent any inverted layer from being formed atthe main surface of semiconductor substrate 1 under assist gates AG1,AG4. Accordingly, the selected memory cell MC is isolated fromnon-selected memory cells MC to prevent information from being writteninto the non-selected memory cells MC.

From inverted layer 23 a thus formed to serve as the source, electronsare discharged toward inverted layer 23 b serving as the drain to injectelectric charge into selected floating gate FG and thereby writeinformation to the selected memory cell MC. Each memory cell MC canstore multivalue data. For the multivalue storage, the voltage appliedto control gate CG is kept constant while the time for writing is variedso as to vary the amount of hot electrons injected into floating gateFG, and thus memory cell MC having several different threshold levelscan be implemented.

FIG. 5 is a cross-sectional view illustrating the read operation ofnonvolatile semiconductor memory device 100. As shown in FIG. 5, in theread operation, to a control gate CG to which a selected memory cell MCis connected, a voltage of approximately 2 V to 5 V for example isapplied. To assist gate AG2 that is adjacent to floating gate FG of theselected memory cell MC and used for forming the source, a voltage ofapproximately 5 V for example is applied. To assist gate AG3 for formingthe drain, a voltage of approximately 5 V for example is applied. On theother hand, to other assist gates AG1, AG4, a voltage of approximately 0V for example is applied.

Accordingly, at the main surface of semiconductor substrate 1 locatedunder assist gate AG2, an inverted layer 23 a serving as the source isformed. At the main surface of semiconductor substrate 1 located underassist gate AG3, an inverted layer 23 b serving as the drain is formed.To inverted layer 23 a thus formed, a voltage of approximately 0 V isapplied and, to inverted layer 23 b, a voltage of approximately 1 V isapplied. On the other hand, at the main surface of semiconductorsubstrate 1 located under other assist gates AG1, AG4, an inverted layeris prevented from being formed so as to implement isolation. Here,depending on the amount of electric charge stored in the selectedfloating gate FG, the threshold voltage of the selected memory cell MCvaries. Therefore, the electric current flowing between inverted layers23 a and 23 b can be sensed to determine information in the selectedmemory cell MC.

Here, as shown in FIGS. 1 and 3, in this nonvolatile semiconductormemory device 100, air gap GA is formed between floating gates FGadjacent to each other in the direction in which assist gates AG extend.Thus, the capacitance formed between floating gates FG adjacent to eachother in the direction in which assist gates AG extend is reduced.Accordingly, even if the amount of electric charge stored in floatinggate FG adjacent to the selected floating gate FG in the direction inwhich assist gates AG extend varies, the influence on the floating gateFG of the selected memory cell MC can be kept small. Thus, variations ofthe threshold voltage of the selected memory cell MC can be suppressed.In this way, the information stored in the selected memory cell MC canaccurately be read.

FIG. 6 is a cross-sectional view of nonvolatile semiconductor memorydevice 100 in the erase operation. As shown in FIG. 6, in the data eraseoperation, a negative voltage of approximately −16 V for example isapplied to a selected control gate CG while a positive voltage isapplied to semiconductor substrate 1. To assist gate AG, a voltage ofapproximately 0 V is applied to prevent an inverted layer from beingformed at the main surface of semiconductor substrate 1. The voltagesare thus applied to cause electric charge stored in the floating gate FGconnected to the selected control gate CG to be discharged intosemiconductor substrate 1 and accordingly information of memory cells MCis erased all together at the same time.

With reference to FIGS. 7 to 15, a method of manufacturing nonvolatilesemiconductor memory device 100 according to the first embodiment isdescribed. FIG. 7 is a cross-sectional view illustrating a first step ofthe manufacturing process of nonvolatile semiconductor memory device 100in the first embodiment. As shown in FIG. 7, normal ion implantation isperformed to selectively introduce phosphorus (P) into a memory regionof semiconductor substrate 1 and thereby form an n-type embedded region.Thereafter, normal ion implantation is performed to selectivelyintroduce boron (B) for example to a peripheral region of semiconductorsubstrate 1 and thereby form a p-type well region. Further, into theperipheral circuit region of semiconductor substrate 1, phosphorus forexample is selectively introduced to form an n-type well region.

Further, on the main surface of semiconductor substrate 1, insulatingfilm 8 made for example of silicon oxide is formed to a thickness ofapproximately 8.5 nm in terms of the thickness of silicon dioxide film,by means of such a thermal oxidation method as ISSG (In-Situ SteamGeneration) oxidation method, and thereafter an electrically conductivefilm 4 made for example of low-resistance polycrystalline silicon isdeposited to a thickness of approximately 50 nm for example by means ofsuch a method as CVD (Chemical Vapor Deposition). Further, on this film,insulating film 10 made for example of silicon nitride is deposited to athickness of approximately 70 nm for example by means of such a methodas CVD. Subsequently, on insulating film 10, an insulating film (thirdinsulating film) 11 made for example of silicon oxide is deposited bysuch a method as CVD using TEOS (Tetraethoxysilane) gas for example andthereafter patterning is carried out. Thus, on the main surface ofsemiconductor substrate 1, a plurality of assist gates AG spaced fromeach other, insulating film 10 on the top surface of assist gates AG andinsulating film 11 on the top surface of insulating film 10 are formed.

FIGS. 8 to 10 are cross-sectional views illustrating second to fourthsteps respectively. As shown in FIG. 8, thermal oxidation is used toform insulating film 9 on the side surface of assist gate AG. Then, asshown in FIG. 9, insulating film 16 is deposited and then dry-etched toform insulating film 16 in the form of the side wall on respective sidesurfaces of insulating film 11, insulating film 10 and insulating film9. At this time, a portion of the main surface of semiconductorsubstrate 1 that is located between the sidewall portions of insulatingfilm 16 is exposed. Then, as shown in FIG. 10, on the main surface ofsemiconductor substrate 1 that is located between the sidewall portionsof insulating film 16, insulating film 15 is formed. Thereafter, on themain surface of semiconductor substrate 1 that is located between thesidewall portions of insulating film 16, an electrically conductive film6 is deposited.

FIGS. 11 and 12 are cross-sectional views illustrating fifth and sixthsteps respectively. As shown in FIG. 11, insulating film 10 is used as astopper to dry-etch insulating film 16 shown in FIG. 10 and therebyexpose most of conductive film 6. Then, as shown in FIG. 12, on thesurface of conductive film 6 located at a higher level than insulatingfilm 16, insulating film 18 is formed. On the top surface of insulatingfilm 18, conductive film CGa of polycrystalline silicon and conductivefilm CGb of such a refractory metal silicide film as tungsten silicide(WSi_(x)) are successively deposited. On the top surface of conductivefilm CGb, an insulating film 13 is formed. It is noted here thatconductive films CGa and CGb are not limited to the above-describedones. Conductive film CGa may be of a material having a weakerionization tendency than conductive film CGb.

FIG. 13 is a cross-sectional view of a portion along assist gates AGshown in FIG. 1 and between assist gates AG formed in theabove-described sixth step. As shown in FIG. 13, in the sixth step,conductive film 6 extends in the direction parallel with the mainsurface of semiconductor substrate 1. FIGS. 14 and 15 arecross-sectional views illustrating seventh and eighth stepsrespectively, showing a portion along assist gates AG and between assistgates AG. As shown in FIG. 14, conductive films CGb, CGa, 6 andinsulating film 18 are patterned to form a conductive-film pattern FGBof the floating gate and a conductive film pattern CGB of the controlgate formed on the top surface of conductive film pattern FGB.Conductive film pattern CGB includes conductive film CGa and conductivefilm CGb that is in contact with conductive film CGa and that is formedon the top surface of conductive film CGa. Between conductive filmpatterns CGB and FGB, insulating film 18 is formed. Then, as shown inFIG. 15, conductive film pattern FGB and conductive film pattern CGB arewet-etched with a higher etch selectivity with respect to the oxidefilm. It is noted that hot water treatment may be used instead of thewet etching.

Here, since conductive film CGb has a stronger ionization tendency thanconductive film CGa and conductive films CGa and CGb are in contact witheach other, an oxidation-reduction reaction occurs between a chemicalsolution and conductive film CGb in the wet etching process so thatconductive film CGb is etched to be reduced in film size in thedirection parallel with the main surface of semiconductor substrate 1.Electrons in conductive film CGa move to conductive film CGb so that anoxidation-reduction reaction between conductive film CGa and thechemical solution is retarded and etching of conductive film CGa issuppressed. On the other hand, since insulating film 18 is formedbetween conductive film pattern FGB and conductive film pattern CGB, itis unlikely that electrons move from conductive film pattern FGB toconductive film pattern CGB so that conductive film pattern FGB isetched to be reduced in film size in the direction parallel with themain surface of semiconductor substrate 1.

In other words, the degree by which conductive film pattern FGB isreduced in film size in the direction parallel with the main surface ofsemiconductor substrate 1 is larger than the degree by which conductivefilm CGa is reduced in film size in the direction parallel with the mainsurface of semiconductor substrate 1. Further, the degree by whichconductive film CGb is reduced in film size in the direction parallelwith the main surface of semiconductor substrate 1 is larger than thedegree by which conductive film CGa is reduced in film size in thedirection parallel with the main surface of semiconductor substrate 1.

In the eighth step, as shown in FIGS. 12, 14 and 15, the side surfacesof conductive film pattern FGB that are opposite to each other in thedirection in which conductive film pattern CGB extends are covered withinsulating film 18. Therefore, the side surfaces of conductive filmpattern FGB that extend in the direction crossing the direction in whichcontrol gate CG as formed extends are etched. Accordingly, the width ofconductive film pattern FGB in the direction crossing the direction inwhich control gate CG as formed extends is decreased, while the width ofconductive film pattern FGB in the direction in which control gate CGextends is maintained. Since insulating film 18 is not etched andconductive film CGa is not substantially etched, insulating film 18remains on the bottom surface of conductive film CGa.

As described above, conductive film pattern FGB is reduced in film sizein the direction parallel with the main surface of semiconductorsubstrate 1, while conductive film CGa is not substantially reduced infilm size. Accordingly, control gate CG as formed has wider portion 28formed to protrude, with respect to floating gate FG as formed, in thedirection parallel with the main surface of semiconductor substrate 1.Further, insulating film 18 that is almost equal in width to widerportion 28 remains on the bottom surface of wider portion 28. Thus,insulating film 18 and conductive film CGa form overhang portion 38 thatprotrudes, with respect to floating gate FG, in the direction parallelwith the main surface of semiconductor substrate 1.

Then, as shown in FIG. 3, interlayer insulating layer 17 is formed byplasma CVD or HDP (High-Density Plasma). Gap-filling conditions of theHDP are set for example to Ar: 150 sccm, O₂: 150 sccm, SiH₄: 80 sccm,LF-RF: 3600 W (900+2700), and HF-RF: 2000 W.

Under the above-described conditions, coverage can be deteriorated andgap-filling capability can be lowered. Thus, filling of the spacebetween floating gates FGa and FGb with interlayer insulating film 17 isretarded while formation of air gap GA is facilitated. In particular,since overhang portions 38 a, 38 b including wider portions 28 a, 28 bare formed on the top surface of floating gates FGa, FGb, interlayerinsulating film 17 is hindered from entering the portion under overhangportions 38 a, 38 b.

Since the distance between overhang portions 38 a and 38 b that is inparallel with the main surface of semiconductor substrate 1 is smallerthan the distance between floating gates FGa and FGb, the space betweenoverhang portions 38 a and 38 b is filled with interlayer insulatingfilm 17 at an early stage so that the space between overhang portions 38a and 38 b is closed. Thus, the space between floating gates FGa and FGbon the main surface of semiconductor substrate 1 is prevented from beingfilled with interlayer insulating film 17 and thus interlayer insulatingfilm 17 is prevented from being formed on the side surfaces of floatinggates FGa, FGb. Moreover, since the space between overhang portions 38 aand 38 b is closed at an early stage, air gap GA is formed betweenfloating gates FGa and FGb. In addition, since overhang portions 38 a,38 b are formed directly on floating gates FGa, FGb, air gap GA isprevented from extending between control gates CG1 and CG2 and extendingto a higher level than control gates CG1, CG2.

Since the space between control gates CG1 and CG2 is filled withinterlayer insulating film 17, it can be prevented that air gap GA isformed in the top surface of interlayer insulating film 17. Thus, in asubsequent cleaning process, a cleaning fluid can be prevented fromentering air gap GA.

As seen from the above, interlayer insulating film 17 may be depositedto the level of the top surface of control gates CG1, CG2, the thicknessof interlayer insulating film 17 can be prevented from excessivelyincreasing. Thus, a contact hole can appropriately be formed ininterlayer insulating film 17 in the process of forming a contact potionwith which a voltage is applied to assist gate AG shown in FIG. 1 and toan inverted layer formed at the main surface of the semiconductorsubstrate that is located under assist gate AG.

The distance between conductive films CGa2 and CGb2 is made larger thanthe distance between overhang portions 38 a and 38 b. Therefore, thespace between conductive films CGa2 and CGb2 is appropriately filledwith interlayer insulating film 17 and a seam is unlikely to be formed.Even if a seam is formed in interlayer insulating film 17 that fills thespace between overhang portions 38 a and 38 b, the seam is preventedfrom extending to the portion between conductive films CGa2 and CGb2Through the process steps as described above, nonvolatile semiconductormemory device 100 is manufactured.

It is noted that, while the first embodiment has been described as theone applied to AG—AND type flash memory, the first embodiment is notlimited to this.

FIG. 33 is a circuit diagram showing a general AND-type flash arrayconfiguration. As shown in FIG. 33, general AND-type flash arrayconfiguration 160 includes a plurality of memory cell transistors 162connected by word lines 164, a select transistor 161 connected to a mainbit line 166 and a select transistor 163 connected to a source line.FIG. 34 is a cross-sectional view of memory cell transistor 162. Asshown in FIG. 34, memory cell transistor 162 has an air gap GA formedbetween floating gates FGa and FGb. With general AND-type flash arrayconfiguration 160 thus formed, the capacitance formed between floatinggates FGa and FGb can be reduced and variations in threshold voltage canbe suppressed.

FIG. 35 is a circuit diagram showing a general NAND-type flash arrayconfiguration 170. As shown in FIG. 35, NAND-type flash arrayconfiguration 170 includes a plurality of select transistors 171connected respectively to bit lines 175, select transistors 173connected to a source line and a plurality of memory cell transistors172 disposed between each select transistor 171 and each selecttransistor 173. FIG. 36 is a detailed cross-sectional view of memorycell transistor 172. As shown in FIG. 36, memory cell transistor 172 hasan air gap GA between floating gates FGa and FGb. With NAND-type flasharray configuration 170 thus formed, the capacitance formed betweenfloating gates FGa and FGb can be reduced. Moreover, effects similar tothose of nonvolatile semiconductor memory device 100 in the firstembodiment can be achieved.

In addition, air gap GA formed between floating gates FGa and FGb toreduce the capacitance between floating gates FGa and FGb is applicableas well to an NOR-type flash array configuration.

Second Embodiment

With reference to FIGS. 16 to 32, a semiconductor device 200 accordingto a second embodiment is described. FIG. 16 is a plan view ofsemiconductor device 200 according to the second embodiment. As shown inFIG. 16, semiconductor device 200 includes a semiconductor substrate 1,an interconnect line L1 formed on a main surface of semiconductorsubstrate 1 and an interconnect line L2 extending along interconnectline L1.

Interconnect line L1 includes a linear portion L1 a extending in thesame single direction and a linear portion L1 b extending from a bentportion L1 c in the direction orthogonal to linear portion L1 a, and isthus formed in the shape of L.

On the top surface of interconnect line L1, an electrically conductivefilm 52 is formed. Conductive film 52 has its width a4 that is in thedirection orthogonal to the direction in which interconnect line L1extends and that is made larger than the width of interconnect line L1.Further, interconnect line L2 includes a linear portion L2 a extendingalong linear portion L1 a and a linear portion L2 b extending from abent portion in the direction orthogonal to linear portion L2 a, and isthus formed in the shape of L.

Interconnect line L2 includes a portion located between an intersectionpoint Lc1 between a normal line extending from bent portion L1 c tolinear portion L2 a and linear portion L2 a and an intersection pointLc2 between a normal line extending from bent portion L1 c to linearportion L2 b and linear portion L2 b, and a distance a3 between thisportion of interconnect line L2 and bent portion L1 c of interconnectline L1 is made larger than a predetermined distance of 90 nm. Further,on the main surface of semiconductor substrate 1 located in the regionsurrounded by the aforementioned portion of interconnect line L2 betweenintersection points Lc1 and Lc2 and by bent portion L1 c, insulatingfilm 55 is deposited.

Interconnect line L2 also includes portions except for the portionbetween intersection points Lc1 and Lc2, and respective distances a1 anda2 between these portions and interconnect line L1 are approximatelyequal to the predetermined distance of 90 nm. On respective top surfacesof the portions except for the portion between intersection points Lc1and Lc2 of interconnect line L2, an electrically conductive film 54 isformed. Here, the portion of interconnect line L2 that is locatedbetween intersection points Lc1 and Lc2 has its width, which isorthogonal to the direction in which interconnect line L2 extends, andthis width is made larger than the width, which is orthogonal to thedirection in which interconnect line L2 extends, of the portions exceptfor the portion between intersection points Lc1 and Lc2 of interconnectline 2.

In insulating film 55 formed on the main surface of semiconductorsubstrate 1 located in the region between interconnect line L1 and theportions except for the portion between intersection points Lc1 and Lc2of interconnect line L2, air gap GA is formed.

FIG. 17 is a plan view of semiconductor device 200 showing a regiondifferent from the region shown in FIG. 16. Interconnect line L1includes a linear portion L1 d, a linear portion L1 f spaced apart fromlinear portion L1 d and a curved portion L1 e connecting linear portionsL1 d and L1 f and curved in the direction away from interconnect lineL2. Interconnect line L2 includes a linear portion L2 d spaced by apredetermined distance from linear portion L1 d and extending alonglinear portion L1 d, a linear portion L2 f spaced by a predetermineddistance from linear portion L1 f and extending along linear portion L1f, and a curved portion L2 e spaced by a predetermined distance fromcurved portion L1 e and curved in the direction away from curved portionL1 e.

Regarding interconnect line L1, on respective top surfaces of linearportion L1 d and linear portion L1 f, conductive film 52 is formed,while conductive film 52 is not formed on the top surface of curvedportion L1 e. Curved portion L1 e is larger in width than linearportions L1 d, L1 f Regarding interconnect line L2, on respective topsurfaces of linear portion L2 d and linear portion L2 f, conductive film54 is formed, while conductive film 54 is not formed on the top surfaceof curved portion L2 e. Curved portion L2 e is larger in width thanlinear portions L2 d and L2 f.

In other words, as shown in FIGS. 16 and 17, there are a region R1 wherethe distance between interconnect line L1 and interconnect line L2 is atleast a predetermined distance, and a region R2 where the distancebetween interconnect line L1 and interconnect line L2 is thepredetermined distance or at most the predetermined distance. In regionR2, on the top surface of interconnect line L1, conductive film 52 isformed and, on the top surface of interconnect line L2, conductive film54 is formed. Further, in region R2, in insulating film 55 filling thespace between interconnect line L1 and interconnect line L2, air gap GAis formed. In region R1, the space between interconnect line L1 andinterconnect line L2 is filled with insulating film 55. Further, inregion R1, on respective top surfaces of interconnect line L1 andinterconnect line L2, conductive films 52 and 54 are not formed.Moreover, respective widths of interconnect line L1 and interconnectline L2 in region R1 are made larger than those of interconnect line L1and interconnect line L2 in region R2.

FIG. 18 is a cross-sectional view along line XVIII-XVIII in FIG. 16,FIG. 19 is a cross-sectional view along line XIX-XIX in FIG. 16 and FIG.20 is a cross-sectional view along line XX-XX in FIG. 17.

As shown in FIG. 18, semiconductor device 200 includes, in region R2shown in FIG. 16, semiconductor substrate 1, insulting film 50 formed onthe main surface of semiconductor substrate 1, interconnect line L1formed on the main surface of semiconductor substrate 1 with insulatingfilm 50 therebetween, interconnect line L2 formed on the main surface ofsemiconductor substrate 1 with insulating film 50 therebetween,conductive film 52 formed on the top surface of interconnect line L1 andlarger in width than interconnect line L1, conductive film 54 formed onthe top surface of interconnect line L2 and larger in width thaninterconnect line L2, and insulating film 55 formed to coverinterconnect line L1 and interconnect line L2. Further, air gap GA isformed to extend from a point on the main surface of semiconductorsubstrate 1 to a level at the bottom surface of conductive film 54 andconductive film 52.

As shown in FIG. 19, in region R1 shown in FIG. 16, conductive film 52is formed on the top surface of interconnect line L1 and conductive film54 is not formed on the top surface of interconnect line L2. Further,the air gap is not formed between interconnect line L1 and interconnectline L2. As shown in FIG. 20, in region R1 shown in FIG. 17, conductivefilms 52 and 54 are not formed on respective top surfaces ofinterconnect lines L1 and L2, and the air gap is not formed ininsulating film 55 located between interconnect lines L1 and L2.

Thus, in region R2 where the distance between interconnect line L1 andinterconnect line L2 is a predetermined distance, air gap GA is formedbetween interconnect lines L1 and L2 to reduce the capacitance betweeninterconnect lines L1 and L2. As the capacitance between interconnectlines L1 and L2 is reduced, for example, variations of an influence onelectric current flowing in interconnect line L2 due to variations incurrent and voltage of interconnection line L1 can be kept small.Further, in region R1 where the distance between interconnect lines L1and L2 is at least a predetermined distance, air gap GA is not formed toprevent air gap GA from being formed in the top surface of insulatingfilm 55.

Further, interconnect lines L1 and L2 located in region R1 haverelatively larger widths respectively to reduce the resistance ofinterconnect lines L1 and L2.

A method of manufacturing semiconductor device 200 structured asdescribed above is now described with reference to FIGS. 21 to 32. FIG.21 is a cross-sectional view illustrating a first step of amanufacturing process of semiconductor device 200, and is across-sectional view along line XVIII-XVIII in FIG. 16. FIG. 22 is across-sectional view illustrating the first step and along line XIX-XIXin FIG. 16. FIG. 23 is a cross-sectional view illustrating the firststep and along line XX-XX in FIG. 17.

As shown in FIGS. 21 to 23, insulating film 50 is formed on the mainsurface of semiconductor substrate 1, an electrically conductive film Lis formed on the top surface of insulating film 50, and an electricallyconductive film 56 is formed on the top surface of conductive film L.Here, as conductive film L, for example, an Al-rich AlCu film having ahigher Al content than conductive film 56 is used. As conductive film56, a Cu-rich AlCu film having a higher Cu content than conductive filmL is used. Conductive film L may be any having a stronger ionizationtendency than conductive film 56. Then, a resist 57 is formed on the topsurface of conductive film 56 and then patterning is carried out.

FIG. 24 is a cross-sectional view illustrating a second step and is across-sectional view subsequent to the step shown in FIG. 21. As shownin FIG. 24, in the portion to be provided as region R2 shown in FIG. 16,a resist 58 is deposited to cover a multilayered body comprised ofpatterned conductive film L and conductive film 56. FIG. 25 is across-sectional view illustrating the second step and is across-sectional view subsequent to the step shown in FIG. 22. As shownin FIG. 25, in the portion to be provided as region R1 of FIG. 16,resist 58 is deposited on the multilayered body to be provided asinterconnect line L1. FIG. 26 is a cross-sectional view illustrating thesecond step and is a cross-sectional view subsequent to the step shownin FIG. 23. As shown in FIG. 26, in region R1 shown in FIG. 17, noresist is formed on the multilayered body that is thus exposed.

FIGS. 27 to 29 are each a cross-sectional view illustrating a thirdstep. As shown in FIG. 27, in the portion to be provided as region R2 ofFIG. 16, conductive film 56 is left on the top surface of conductivefilm L. As shown in FIG. 28, in the portion to be provided as region R1of FIG. 16, conductive film 56 formed on the top surface of conductivefilm L to be provided as interconnect line L2 is removed. Further, asshown in FIG. 29, in the portion to be provided as region R1 shown inFIG. 17, conductive film 56 is removed from both of conductive films Lto be provided as interconnect lines L1 and L2 respectively.

FIGS. 30 to 32 are each a cross-sectional view illustrating a fourthstep. In the fourth step illustrated in FIGS. 30 to 32, wet etching isperformed to form interconnect lines L1 and L2. Instead of the wetetching, a chemical solution containing ammonia hydroxide-hydrogenperoxide-water mixture may be used. Then, as shown in FIG. 30, themultilayered body shown in FIG. 27 is wet-etched so that conductive filmL is mainly etched while conductive film 56 is not substantially etched,since conductive film L has a stronger ionization tendency thanconductive film 56. Therefore, in the portion to be provided as regionR2 shown in FIG. 16, interconnect line L1 and interconnect line L2 eachsmaller in width than conductive film 56 are formed under the bottomsurface of conductive film 56.

As shown in FIG. 31, on the top surface of conductive film L to beprovided as interconnect line L1, conductive film 56 is formed.Therefore, in a chemical solution for wet etching, anoxidation-reduction reaction occurs between this conductive film L andthe chemical solution and electrons in conductive film 56 move intoconductive film L. Accordingly, etching of conductive film L to beprovided as interconnect line L1 is promoted. On the other hand, anoxidation-reduction reaction occurs between conductive film L to beprovided as interconnect line L2 and the chemical solution so thatconductive film L is etched. Here, since conductive film 56 is notformed on the top surface of this conductive film L, the etching ratefor conductive film L to be provided as interconnect line L2 is lowerthan that of conductive film L to be provided as interconnect line L1.

Thus, interconnect line L2 has a portion having its top surface on whichconductive film 56 is not formed and this portion is formed with alarger width than that of interconnect line L1 with conductive film 56formed thereon. Further, as shown in FIG. 32, in the region to beprovided as region R1 shown in FIG. 17, conductive film 56 is not formedon conductive films L to be provided as interconnect lines L1 and L2respectively. Therefore, respective widths of interconnect lines L1 andL2 as formed are larger than those of interconnect lines L1 and L2having conductive film 56 formed thereon as shown in FIG. 30.

Subsequently, as shown in FIGS. 18 to 20, insulating film 55 isdeposited. In region R2 shown in FIG. 16, conductive film 56 larger inwidth than interconnect lines L1 and L2 is formed on respective topsurfaces of interconnect lines L1 and L2 as shown in FIG. 30. Therefore,insulating film 55 is hindered to a certain degree from being depositedon the main surface of semiconductor substrate 1 in the region locatedbetween interconnect lines L1 and L2. On the other hand, since thedistance between respective conductive films 56 formed on respective topsurfaces of interconnect lines L1 and L2 is made smaller than thedistance between interconnect lines L1 and L2, the space between thoseconductive films 56 is closed by insulating film 55. Therefore, inregion R2 shown in FIG. 16, air gap GA is formed in insulating film 55in the region located between interconnect lines L1 and L2.

In region R1 shown in FIG. 16, conductive film 56 larger in width thaninterconnect line L1 is formed on interconnect line L1 while conductivefilm 56 is not formed on interconnect line L2 as shown in FIG. 31.Therefore, insulating film 55 is deposited on the main surface ofsemiconductor substrate 1 in the region located between interconnectlines L1 and L2. As shown in FIG. 19, the space between interconnectlines L1 and L2 is filled with insulating film 55. Further, in region R1shown in FIG. 17, conductive film 56 is not formed on respective topsurfaces of interconnect lines L1 and L2 as shown in FIG. 32. Therefore,insulating film 55 is appropriately deposited on the main surface ofsemiconductor substrate 1 in the region located between interconnectlines L1 and L2. Therefore, as shown in FIG. 20, the space betweeninterconnect lines L1 and L2 is filled with insulating film 55. Throughthe steps as described above, semiconductor device 200 can bemanufactured.

The present invention is suitable for the nonvolatile semiconductormemory device, the semiconductor device and the method of manufacturinga nonvolatile semiconductor memory device.

Although the present invention has been described and illustrated indetail, it is clearly understood that the same is by way of illustrationand example only and is not to be taken by way of limitation, the spiritand scope of the present invention being limited only by the terms ofthe appended claims.

1-9. (canceled)
 10. A method of manufacturing a semiconductor device comprising: forming a first interconnect line on a main surface of a semiconductor substrate with a first electrically insulating film therebetween; forming a second interconnect line on the main surface of said semiconductor substrate with a second electrically insulating film therebetween to extend along said first interconnect line; forming a first electrically conductive film on a top surface of said first interconnect line such that the first electrically conductive film is larger than said first interconnect line in width in the direction parallel with the main surface of said semiconductor substrate; forming a second electrically conductive film on a top surface of said second interconnect line such that the second electrically conductive film is larger than said second interconnect line in width in the direction parallel with the main surface of said semiconductor substrate; forming a third electrically insulating film to cover said first electrically conductive film and said second electrically conductive film; forming a first region where the distance between said first interconnect line and said second interconnect line is at most a predetermined value; forming a second region where the distance between said first interconnect line and said second interconnect line is larger than said predetermined value; and forming a gap that is in said first region where said first electrically conductive film and said second electrically conductive film are formed and that is formed in said third electrically insulating film between said first interconnect line and said second interconnect line located in said first region.
 11. The method according to claim 10, wherein said first interconnect line and said first electrically conductive film contact each other, said second interconnect line and said second electrically conductive film contact each other, said first electrically conductive film is weaker in ionization tendency than said first interconnect line, and said second electrically conductive film is weaker in ionization tendency than said second interconnect line. 